The present invention relates generally to memory testing, and more specifically to long write testing of memory chips.
Writing to a memory cell or cells of memories, such as Static Random Access Memories (SRAMs), multiple port memories, and First In First Out (FIFO) memories, can sometimes adversely affect adjacent memory cells on the same column that share a bitline. These adjacent memory cells should not be affected if their wordlines are off; however, leakage from a memory cell node to a bitline may be sufficient to overcome the pull-up resistance of an adjacent non-selected memory cell, causing the data of that memory cell to become corrupted. This problem is exacerbated when memory cells are subjected to a long write cycle, because there is greater opportunity for such leakage to occur by virtue of the length of the write cycle. Therefore, memory cell node to bitline leakage and subsequent corruption of adjacent non-selected memory cells is often a concern during long write testing of a memory device.
Long write testing is typically conducted after writing a test data pattern to selected memory cells of a memory device. The leakage problem associated with a long write test occurs when writing to memory cells along a column and inadvertently affecting non-selected memory cells, whose wordlines are off. The non-selected memory cells that are affected experience leakage from the memory cell node to a bitline which causes them to erroneously change state. The write cycle during a long write test is typically quite long, thereby increasing the probability that the leakage problem will occur.
Unfortunately, the test modes which may be used to screen for bitline to cell leakage may introduce additional problems. Such test modes may themselves adversely affect the long write test by introducing large switching transients. For instance, after the wordlines of all memory cells of a memory device are turned off, a test mode may simultaneously pull down either bitline true or bitline complement in order to "disturb" the memory cells. The memory cells may then be read following the disturb condition to check for errors in the states of individual memory cells. However, the act of simultaneously pulling large numbers of bitlines to a given logic state necessarily introduces large current switching transients. Additionally, memory cell recovery time of disturbed memory cells following such stress testing may be of an undesirably long duration.
Thus, there exists an unmet need in the art to be able to perform a long write test of a memory device in a manner that effectively identifies leakage problems while also minimizing long write test time, current switching transients, and memory cell recovery time.